The demand for computing devices continues to rise, even as the demand for computing devices to achieve higher performance also rises. However, conventional electrical I/O (input/output) signaling is not expected to keep pace with the demand for performance increases. Poor scaling of bandwidth density (GB/s/mm), aggregate bandwidth (e.g., GB/s), and power efficiency (mW/Gb/s) or energy per bit (pJ/b) for conventional (electrical) I/O signaling are not expected to meet demands for future computing performance.
I/O signals are sent electrically from the processor (e.g., CPU—central processing unit) through the processor package (or just package), socket (which is sometimes not present), and board to electrical cables and/or backplanes. Current state-of-the art for electrical I/O signals between the processor and the processor package (i.e., the package in which the processor die is housed) is to use electrical connections formed by flip-chip processing (Cu bumps and solder). Electrical signals between the package and the board are also electrical in nature, and are transmitted via solder joints (in the case of BGA—ball grid array) or via a socket with pins connected to the board by solder joints (in the case of LGA—land grid array). The board communicates to the external world through connectors that mate to cables, which can be electrical or optical. In the case of Blade Servers used in Data Centers, multiple boards connect to a backplane, which in turn connects to electrical and/or optical cables.
The maximum rate that electrical I/O signals can reach, which is limited by electrical connectors, package, and board traces, is estimated at approximately 20-25 Gb/s for distances above 1 m. In addition, the need for equalization and the high losses of package and board traces and connectors result in poor scaling of energy per bit. Furthermore, the total bandwidth density is also limited by bump pitch, as well as package and board traces. Electrical I/O is not expected to meet the requirements for many applications of High Performance Computing (HPC).
While the use of photonic components finds increasing use in computing devices, current optical signaling solutions are not scalable to the level of taking greater advantage of the potential advantages of optical communication. The use of optical signals in device communication has significant potential advantages over electrical communication, namely in terms of power and theoretical bandwidth, bandwidth density, and aggregate throughput over a distance. However, the inability to cost efficiently scale the solutions prevents current optical systems from meeting the requirements of many HPC applications.
An alternative to electrical signaling in use today is based on optical cables that receive an electrical signal and convert it to optical. Such cables typically use directly-modulated VCSELs (vertical cavity surface-emitting lasers), which currently are limited to 10 Gb/s with 4 transmitter/receiver links, i.e., an aggregate bandwidth of 80 Gb/s=10 GB/s. The signaling rate is limited by the speed of the VCSEL, which is expected not to exceed 25 Gb/s in the near future.
In addition to the limits on current optical cable solutions, current optical signaling terminates far from the processor, which requires electrical-optical conversion and electrical transfer that creates a bottleneck to the processor, and results in power penalties. Serial connections to the processor are too slow to take advantage of the optical signaling throughput capabilities, and parallel connections to the processor require a significant amount of board real estate and pins to the processor package. In addition, the current components used in the optical signaling and electrical-optical coupling do not scale in a way that is usable with high-volume manufacturing.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.